IEEE SSCS Oregon Chapter June Meeting and Seminar

Join us for a (virtual) talk from SSCS Distinguished Lecturer Yvain Thonnart from CEA-Leti, Grenoble, France, on Thursday, June 15th. The seminar will be held from 8:00am to 9:30am (PST) via a Virtual format. Please register for the meeting link and information.

Register via the included Zoom link. You need to register via Zoom (not vTools) to be able to join the meeting.

Topic:

On-chip communication : from architectures to circuits

Abstract:

On-chip communication directly impacts the performance, energy efficiency, and area of systems-on-chip, multi-processors and highly-parallel accelerators, especially for emerging machine learning applications. In this talk, I will introduce a range of design options for on-chip interconnects, from point-to-point links to complex network topologies, starting from architecture to low-level circuit techniques. The presentation addresses base routing schemes and mapping of different protocol families, such as data-flow or address-map based communication. Moving on to microarchitecture, it presents flow-control and arbitration requirements and options. I will then detail circuit-level considerations, with a focus on different synchronization strategies across multiple clock domains, including multi-synchronous, source-synchronous-clocking, and fully-asynchronous circuits, to finally introduce the potential of 3D-chip integration for on-chip communication.

Speaker Biography:

Yvain Thonnart received the MS degree from Ecole Polytechnique and an engineering diploma from Telecom Paris, France in 2005. He then joined the Technological Research Division of CEA, the French French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute. He has led the development of several large research projects for on-chip communications, focusing on the maturation of novel concepts towards industrial adoption, such as communication between multiple voltage and frequency domains, 3D-stacked circuits, and optical on-chip interconnects, leading to more than 70 publications and 10 patents. He is now senior expert on communication and synchronization in systems on chip, and scientific advisor for the mixed-signal design lab. His main research interests include asynchronous logic, networks on chip, physical implementation, emerging technologies integration such as photonics, cryoelectronics and interposers. He is currently serving in the technical program committee of the ISSCC.