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fixing date 2021-06-04 09:00:00 US/Pacific

fixing date 2021-06-04 10:00:00 US/Pacific

fixing date 2021-06-08 18:30:00 US/Pacific

fixing date 2021-06-08 20:30:00 US/Pacific

4 meetings

Title:
IEEE Oregon Section June VIRTUAL Meeting IF YOU DID NOT ALREADY GET THE INVITATION, REGISTER TO GET THE MEETING LINK
Date:
June 8th
6:30 PM (2 hours)
Location:
5404 NE 70th Circle
Portland
Abstract:

This is our monthly Executive Committee Meeting

Title:
IEEE SD Joint APS/CAS/EDS/MTTS/SSCS chapter Seminar: Design-Technology Co-Optimization for Reliability and Quality in Advanced Nodes
Date:
June 4th
9:00 AM (1 hour)
Location:
Portland
Abstract:

DATE/TIME 
Friday, June 4, 2021 @ 9:00-10:00am PDT

 

TITLE
Design-Technology Co-Optimization for Reliability and Quality in Advanced Nodes

 

WEBEX
https://ieeemeetings.webex.com/ieeemeetings/onstage/g.php?MTID=efc93046c646a65c952a62755f6f9dd24

 

ABSTRACT
Semiconductor demand is rapidly expanding beyond the computing and mobile markets with more products being introduced for automotive, industrial, medical, avionics, and space applications. Chips are increasingly complex with growing functionality through integration of more digital, analog/mixed-signal, and RF sub-systems. Technologies still continue to scale to ever-shrinking dimensions with novel materials and device architectures to realize new power-performance-area levels. Although these new capabilities enable diversified product opportunities, guaranteeing reliability and quality over long product lifetimes has become increasingly challenging in such applications. This paper provides an overview of reliability and product quality challenges in advanced CMOS nodes comprising finFET and fully depleted silicon-on-insulator technologies. Following an overview of intrinsic and extrinsic reliability mechanisms along with design and test methodologies for improving reliability and product quality, it addresses key reliability challenges in fully depleted technologies, such as self-heating, I/O scaling, middle-of-line reliability, dielectric-breakdown monitoring, variation, and stochastic aging. To meet these more stringent requirements in advanced technologies, chip designers and manufacturers must collaboratively optimize chip process technology, design, and test in an even more cohesive and transparent partnership.

BIOGRAPHY
Mehul Shroff works at NXP Semiconductors in Austin, TX, in the Silicon Reliability group, and is primarily focused on advanced-CMOS and NVM technologies. He has over 25 years of experience in the semiconductor industry. His prior experience includes process integration and device engineering in manufacturing, technology transfer, and development, module development, yield engineering, and test vehicles and test structures. His current interests are focused on reliability tools and methodologies and design for reliability. He holds graduate degrees in Chemical Engineering and Software Engineering.

Title:
Turtlebot3 Burger Build 04
Date:
May 18th
6:30 PM (2 hours)
Abstract:

Robert Adams will guide us through using Docker images to hold node library dependencies (buildx, multi-arch).

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Title:
IEEE PES OREGON CHAPTER MAY 18 MEETING
Date:
May 18th
12:30 PM (2 hours)
Location:
Portland
Abstract:

Please join us for the May meeting of the PES Oregon Section

We will be having a guest speaker this month

Our speaker will be Mr. Frank Afranji

Frank is the President of the Northwest Power Pool where he is responsible for the management and coordination of various programs and services provided by the Power Pool.

4 meetings. Generated Tuesday, June 15 2021, at 5:46:55 AM. All times America/Los_Angeles